1. Field of the Invention
The present invention relates to a current type inverter circuit, a current type logic circuit using the same, a current type latch circuit using a current type inverter circuit, a semiconductor integrated circuit using a current type inverter circuit, a current type ring oscillator using a current type inverter circuit, a voltage-controlled oscillator using a current type inverter circuit and a PLL circuit using a current type inverter circuit.
2. Description of the Background Art
FIG. 47 is a circuitry diagram showing a structure of a conventional biasing CMOS inverter circuit. In FIG. 47, the CMOS inverter circuit is formed by an inverter part 100 and a bias circuit part 101.
In the inverter part 100, PMOS transistors Q201 and Q202 and NMOS transistors Q203 and Q204 are connected in series to each other between a power source VDD and a ground level. A bias voltage PBIAS is applied to a gate of the PMOS transistor Q201 while a bias voltage NBIAS is applied to a gate of the NMOS transistor Q204. Gates of the PMOS transistor Q202 and the NMOS transistor Q203 are connected in common.
In the bias circuit part 101, a current mirror circuit is formed by PMOS transistors Q205 and Q206 which share a gate. A source of the PMOS transistor Q205 is connected to the power source VDD while a gate and a drain of the PMOS transistor Q205 are grounded through a reference current source 102. A drain of the PMOS transistor Q206 is connected to a gate and a drain of the NMOS transistor Q207. A source of the NMOS transistor Q207 is grounded.
A gate voltage of the transistors Q205 and Q206 is supplied to the inverter part 100 as the bias voltage PBIAS, while a gate voltage of the transistor Q207 is supplied to the inverter part 100 as the bias voltage NBIAS.
In this structure, biasing in the inverter part 100 of the CMOS inverter circuit is set by the bias voltage PBIAS and the bias voltage NBIAS which are set in the bias circuit part 101. An input signal IN is supplied to the gates of the PMOS transistor Q202 and the NMOS transistor Q203 in the inverter part 100. From the drains of PMOS transistor Q202 and the NMOS transistor Q203, as an output signal OUT, the inverter part 100 outputs a signal which is obtained by reversing the logic value of the input signal IN.
The conventional logic circuit of FIG. 47 such as a CMOS inverter which operates in response to a voltage signal transmits information "1" and "0" when the input signal IN and the output signal OUT swing a full range from the ground level (0 V) to the power source voltage level. Due to this constraint, the conventional logic circuit cannot operate at a high speed. Further, when the input signal IN has an intermediate voltage, the conventional logic circuit carries a through current, which unnecessarily uses a consumption power.